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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
IDTCV125
FEATURES:
* Power management control suitable for notebook applications * One high precision PLL for CPU, SSC and N programming * One high precision PLL for SRC/PCI, supports 100MHz output frequency, SSC and N programming * One high precision PLL for LVDS. Supports 100/96MHz output frequency, SSC programming * One high precision PLL for 96MHz/48MHz * Band-gap circuit for differential outputs * Support spread spectrum modulation, -0.5 down spread and others * Support SMBus block read/write, index read/write * Selectable output strength for REF * Allows for CPU frequency to change to a slower frequency to conserve power when an application is less executionintensive * Smooth transition for N programming * Available in TSSOP package
IDTCV125 is a 56 pin clock device, incorporating both Intel CK410M and CKSSCD requirements, for Intel advance P4 processors. The CPU output buffer is designed to support up to 400MHz processor. This chip has four PLLs inside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Static PLL frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/LVDS has its own Spread Spectrum selection.
DESCRIPTION:
OUTPUTS:
* * * * * * *
KEY SPECIFICATION:
* * * *
2*0.7V current -mode differential CPU CLK pair 6*0.7V current -mode differential SRC CLK pair One CPU_ITP/SRC selectable CLK pair 6*PCI, 2 free running, 33.3MHz 1*96MHz, 1*48MHz 1*REF One 100/96 MHz differential LVDS
CPU/SRC CLK cycle to cycle jitter < 85ps PCI CLK cycle to cycle jitter < 250ps Static PLL frequency divide error < 114 ppm Static PLL frequency divide error for 48MHz < 5 ppm
FUNCTIONAL BLOCK DIAGRAM
PLL1 SSC N Programmable
CPU CLK Output Buffer Stop Logic
CPU[1:0]
X1
XTAL Osc Amp
CPU_ITP/SRC7 IREF REF LVDS CLK Output Buffer Stop Logic ITP_EN LVDS
X2
SDATA SCLK
SM Bus Controller
PLL2 SSC
IREF
PLL3 SSC N Programmable VTT_PWRGD#/PD SEL100/96# FSA.B.C PCI_STOP# CPU_STOP# Control Logic SEL 100/96MHz
SRC CLK Output Buffer Stop Logic
SRC[6:1] PCI[3:0], PCIF[1:0]
IREF
48MHz PLL4 48MHz/96MHz Output BUffer DOT96
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
(c) 2004 Integrated Device Technology, Inc.
DECEMBER 2004
DSC 6552/14
IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
VDD_PCI VSS_PCI
PCI1 PCI2 PCI3
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage GND - 0.5 Storage Temperature Ambient Operating Temperature Case Temperature Input ESD Protection Human Body Model
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Min
Max 4.6 4.6 +150 +70 +115
Unit V V C C C V
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8
5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9
PCI0
VDDA VDDIN TSTG TAMBIENT TCASE ESD Prot
PCI_STOP# CPU_STOP# FSC/TEST_SEL REF VSS_REF XTAL_IN XTAL_OUT VDD_REF SDA SCL VSS_CPU
CPU0 CPU0#
-65 0 2000
VSS_PCI VDD_PCI PCIF0/ITP_EN
(1)
PCIF1/SEL100/96# VTT_PWRGD#/PD VDD48
USB48/FSA
VSS48
DOT96 DOT96#
VDD_CPU
CPU1 CPU1#
FSB/TEST_MODE
(2) (2)
LVDS
LVDS# SRC1 SRC1#
IREF VSSA VDDA
CPU2_ITP/SRC7 CPU2_ITP#/SRC7#
VDD_SRC
SRC2 SRC2# SRC3 SRC3# SRC4 SRC4#
VDD_SRC
SRC6 SRC6# SRC5 SRC5#
VDD_SRC
VSS_SRC
NOTES: 1. 130K internal pull-up resistor. 2. Can be configured as 100MHz or 96MHz output clock, depending on pin9 power on pull-up (100MHz) or pull-down (96MHz) latch. If using internal pull-up resistor, power on would be 100MHz.
TSSOP TOP VIEW
FREQUENCY SELECTION TABLE
FSC, B, A 101 001 011 010 000 100 110 111 CPU 100 133 166 200 266 333 400 Reserve SRC[7:0] 100 100 100 100 100 100 100 100 PCI 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 2 USB 48 48 48 48 48 48 48 48 DOT 96 96 96 96 96 96 96 96 REF 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Number 1 2 3 4 5 6 7 8 9 10 Name VDD_PCI VSS_PCI PCI1 PCI2 PCI3 VSS_PCI VDD_PCI PCIF0/ITP_EN PCIF1/SEL100/96# VTT_PWRGD#/PD Type PWR GND OUT OUT OUT GND PWR I/O I/O IN 3.3V GND PCI clock PCI clock PCI clock GND 3.3V PCI clock, free running. CPU2 select (sampled on VTT_PWRGD# assertion) HIGH = CPU2. PCI clock, free running. SEL100/96MHz (sampled on VTT_PWRGD# assertion) HIGH, LVDS = 100MHz. Level-sensitive strobe used to latch the FSA, FSB, FSC/TEST_SEL, and PCIF0/ITP_EN inputs. After VTT_PWRGD# assertion, becomes a real-time input for asserting power down. (Active HIGH). Latch PCIF1/ SEL100/96# input. 3.3V 48MHz clock/FSA for CPU frequency selection GND 96MHz 0.7 current mode differential clock output 96MHz 0.7 current mode differential clock output CPU frequency selection. Selects REF/N or Hi-Z when in test mode, Hi-Z = 1, REF/N = 0. Differential serial reference clock Differential serial reference clock Differential serial reference clock Differential serial reference clock 3.3V Differential serial reference clock Differential serial reference clock Differential serial reference clock Differential serial reference clock Differential serial reference clock Differential serial reference clock 3.3V GND Differential serial reference clock Differential serial reference clock Differential serial reference clock Differential serial reference clock 3.3V Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7#. Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7. 3.3V GND Reference current for differential output buffer Host 0.7 current mode differential clock output Host 0.7 current mode differential clock output 3.3V Description
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
VDD48 USB48/FSA VSS48 DOT96 DOT96# FSB/TEST_MODE LVDS LVDS# SRC1 SRC1# VDD_SRC SRC2 SRC2# SRC3 SRC3# SRC4 SRC4# VDD_SRC VSS_SRC SRC5# SRC5 SRC6# SRC6 VDD_SRC CPU2_ITP#/SRC7# CPU2_ITP/SRC7 VDDA VSSA IREF CPU1# CPU1 VDD_CPU
PWR I/O GND OUT OUT IN OUT OUT OUT OUT PWR OUT OUT OUT OUT OUT OUT PWR GND OUT OUT OUT OUT PWR OUT OUT PWR GND OUT OUT OUT PWR
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONT.)
Pin Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Name CPU0# CPU0 VSS_CPU SCL SDA VDD_REF XTAL_OUT XTAL_IN VSS_REF REF FSC/TEST_SEL CPU_STOP# PCI_STOP# PCI0 Type OUT OUT GND IN I/O PWR OUT IN GND OUT IN IN IN OUT Host 0.7 current mode differential clock output Host 0.7 current mode differential clock output GND SM bus clock SM bus data 3.3V XTAL output XTAL input GND 14.318 MHz reference clock output CPU frequency selection. Selects test mode if pulled above 2V when VTT_PWRGD# is asserted LOW. Stop all stoppable CPU CLK Stop all stoppable PCI, SRC CLK PCI clock Description
INDEX BLOCK WRITE PROTOCOL
Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N (0 is not valid) Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop
INDEX BLOCK READ PROTOCOL
Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 38 39-46 47 48-55 # of bits 1 8 1 8 1 1 8 1 8 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave Master Slave Master Slave
Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit30-37).
Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3h Ack (Acknowledge) Byte count, N (block read back of N bytes), power on is 8 Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop
Master Slave Master
INDEX BYTE WRITE
INDEX BYTE READ
Setting bit[11:18] = starting address, bit[20:27] = 01h.
Setting bit[11:18] = starting address. After reading back the first data byte, master issues Stop bit.
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
SSC MAGNITUDE CONTROL FOR CPU, SRC, AND SMC
SMC[2:0] 000 001 010 011 100 101 110 111 -0.25 -0.5 -0.75 -1 0.125 0.25 0.375 0.5
RESOLUTION
CPU (MHz) 100 133 166 200 266 333 400 Resolution 0.666667 0.666667 1.333333 1.333333 1.333333 2.666667 2.666667 N= 150 200 125 150 200 125 150
SEL 100/96# CONFIGURATION
SEL 100/96# 0 1 LVDS Frequency 96 100 Unit MHz MHz
SPREAD SPECTRUM CONTROL SELECTION (SSC) FOR LVDS
S[3:0] 0000 0001 0010 0011 Spread -0.8% -1% -1.25% -1.5% -1.75% -2% -0.3% -0.5% 0.3% 0.4% 0.5% 0.6% 0.8% 1% 1.25% 1.5%
S.E. CLOCK STRENGTH SELECTION (PCI, REF, USB48)
Str[1:0] 00 01 10 11 Level 1 0.8 0.6 1.2
0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
CONTROL REGISTERS
N PROGRAMMING PROCEDURE
* *
Use Index byte write. For N programming, the user only needs to access Byte 11, Byte 12, and Byte 9. 1. 2. 3. Write Byte 11 for CPU PLL N, CPU f = N* Resolution (see resolution table). Write Byte 12 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3. Enable N Programming bit, Byte 9 bit 1. Once this bit is enabled, any N value will be changed on the fly.
BYTE 0
Bit 0 1 2 3 4 5 6 7 Output(s) Affected Reserved SRC1, SRC1# SRC2, SRC2# SRC3, SRC3# SRC4, SRC4# SRC5, SRC5# SRC6, SRC6# CPU2, CPU2#/ SRC7, SRC7# Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Tristate Tristate Tristate Tristate Tristate Tristate Tristate Enable Enable Enable Enable Enable Enable Enable RW RW RW RW RW RW RW 1 1 1 1 1 1 1 Description/Function 0 1 Type Power On
BYTE 1
Bit 0 1 2 3 4 5 6 7 Output(s) Affected CPU[2:0], SRC[7:1], PCI[5:0], PCIF[1:0] CPU0, CPU0# CPU1, CPU1# Reserved REF USB48 DOT96 PCIF0 Output Enable Output Enable Output Enable Output Enable Tristate Tristate Tristate Tristate Enable Enable Enable Enable Output Enable Output Enable Tristate Tristate Enable Enable RW RW RW RW RW RW RW 1 1 0 1 1 1 1 Description/Function Spread Spectrum mode enable 0 Spread off 1 Spread on Type RW Power On 0
BYTE 2
Bit 0 1 2 3 4 5 6 7 Output(s) Affected PCIF1 Reserved PCI0 PCI1 PCI2 PCI3 Reserved Reserved Output Enable Output Enable Output Enable Output Enable Tristate Tristate Tristate Tristate Enable Enable Enable Enable Description/Function Output Enable 0 Tristate 1 Enable Type RW RW RW RW RW RW RW RW Power On 1 1 1 1 1 1 1 1
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 3
Bit 0 1 2 3 4 5 6 7 Output(s) Affected Reserved SRC1 SRC2 SRC3 SRC4 SRC5 SRC6 SRC7 Description / Function 0 1 Type RW RW RW RW RW RW RW RW Power On 0 0 0 0 0 0 0 0
Allow controlled by PCI_STOP# assertion
Free running, not affected by PCI_STOP#
Stopped with PCI_STOP#
BYTE 4
Bit 0 1 2 3 4 5 6 7 Output(s) Affected CPU0, CPU0# CPU1, CPU1# CPU2, CPU2# PCIF0 PCIF1 Reserved DOT96 Reserved DOT96 power down drive mode Driven in power down Tristate Description / Function Allow control of CPU0 with assertion of CPU_STOP# Allow control of CPU1 with assertion of CPU_STOP# Allow control of CPU2 with assertion of CPU_STOP# Allow controlled by PCI_STOP# assertion 0 Not stopped by CPU_STOP# Not stopped by CPU_STOP# Not stopped by CPU_STOP# Not stopped by PCI_STOP# 1 Stopped with CPU_STOP# Stopped with CPU_STOP# Stopped with CPU_STOP# Stopped with PCI_STOP# Type RW RW RW RW RW RW RW RW Power On 1 1 1 0 0 0 0 0
BYTE 5
Bit 0 1 2 3 4 5 6 7 Output(s) Affected CPU0, CPU0# CPU1, CPU1# CPU2, CPU2# SRC[7:1], SRC[7:1]# CPU0, CPU0# CPU1, CPU1# CPU2, CPU2# SRC[7:1], SRC[7:1]# Description / Function CPU0 PD drive mode CPU1 PD drive mode CPU2 PD drive mode SRC PD drive mode CPU0 CPU_STOP drive mode CPU1 CPU_STOP drive mode CPU2 CPU_STOP drive mode SRC PCI_STOP drive mode 0 Driven in power down Driven in power down Driven in power down Driven in power down Driven in CPU_STOP# Driven in CPU_STOP# Driven in CPU_STOP# Driven in PCI_STOP 1 Tristate in power down Tristate in power down Tristate in power down Tristate in power down Tristate when stopped Tristate when stopped Tristate when stopped Tristate when stopped Type RW RW RW RW RW RW RW RW Power On 0 0 0 0 0 0 0 0
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 6
Bit 0 1 2 3 Output(s) Affected CPU[2:0] CPU[2:0] CPU[2:0] PCI, SRC Description / Function FSA latched value on power up FSB latched value on power up FSC latched value on power up Software PCI_STOP control for PCI and SRC CLK REF drive strength Test clock mode entry control CPU, SRC, PCI PCIF, REF, USB48, DOT96 Only valid when Byte 6, Bit 6 is HIGH Stop all PCI, PCIF, and SRC which can be stopped by PCI_STOP# 1x drive Normal operation Hi-Z Software STOP Disabled 2x drive Test mode, controlled by Byte 6, Bit 7 REF/N 0 1 Type R R R RW 1 Power On
4 5 6 7
REF Reserved
RW RW RW RW
1 0 0 0
BYTE 7
Bit 0 1 2 3 4 5 6 7 Output(s) Affected Description / Function Vendor ID Vendor ID Vendor ID Vendor ID Revision ID Revision ID Revision ID Revision ID 0 1 Type R R R R R R R R Power On 1 0 1 0 0 0 0 0
BYTE 8, LVDS CONTROL BYTE
Bit 0 1 2 3 4 5 6 7 Output(s) Affected LVDS LVDS SSC EN LVDS Enable SEL 100/96# S3 S2 S1 S0 Description/Function HW/ SMBus control Spread spectrum enable Output Enable Select LVDS frequency see SSC table see SSC table see SSC table see SSC table 0 HW(1) Off Disable 96MHz 1 SW On Enable 100MHZ Type RW RW RW RW RW RW RW RW Power On 0 1 1 SEL 100/96# 0 0 0 0
NOTE: 1. If bit 0 is set to 0, LVDS output frequency is selected by HW SEL 100/96#. If bit 0 is set to 1, LVDS output frequency is selected by bit 3.
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 9
Bit 0 1 2 3 4 5 6 7 Output(s) Affected One cycle read N Programming enable LVDS PLL power down USB PLL power down SRC PLL power down CPU PLL power down Only valid when Byte1 bit0 is 1 Description / Function 0 disable Disable normal normal normal normal disable 1 enable enable Power down Power down Power down Power down enable Type RW RW RW RW RW RW RW RW Power On 0 0 0 0 0 0 0 1
SRC, PLL2, SSC enable
BYTE 10
Bit 0 1 2 3 4 5 6 7 Output(s) Affected SRC SMC0 SRC SMC1 SRC SMC2 Reserved CPU SMC0 CPU SMC1 CPU SMC2 Reserved Description / Function SRC/PCI SSC control see SMC table 0 1 Type RW RW RW RW RW RW RW RW Power On 1 0 0 0 1 0 0 0
CPU PLL SSC control see SMC table
BYTE 11
Bit 0 1 2 3 4 5 6 7 Output(s) Affected CPU_N0, LSB CPU_N1 CPU_N2 CPU_N3 CPU_N4 CPU_N5 CPU_N6 CPU_N7, MSB Description / Function CPU CLK = N* Resolution see Resolution table 0 1 Type RW RW RW RW RW RW RW RW Power On 0 1 1 0 1 0 0 1
BYTE 12
Bit 0 1 2 3 4 5 6 7 Output(s) Affected SRC_N0, LSB SRC_N1 SRC_N2 SRC_N3 SRC_N4 SRC_N5 SRC_N6 SRC_N7, MSB Description / Function 0 1 Type RW RW RW RW RW RW RW RW Power On 0 1 1 0 1 0 0 1
SRC f = N*SRC Resolution Resolution = 0.666667 100MHz N= 150
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 13
Bit 0 1 2 3 4 5 6 7 Output(s) Affected 48MHzStr0 48MHStr1 REFStr0 REFStr1 PCIStrC0 PCIStrC1 PCIFStr0 PCIFStr1 Description / Function USB48MHz0 strength selection REF strength selection PCI strength selection PCIF strength selection 0 1 Type RW RW RW RW RW RW RW RW Power On 0 0 0 0 0 0 0 0
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT PARAMETERS
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%
Symbol VIH VIL VIH_FS VIL_FS IIH IIL1 IIL2 IDD3.3OP IDD3.3PD FI LPIN CIN COUT CINX COUTX TSTAB Clock Stabilization(2,3) Modulation Frequency(2) TDRIVE_SRC(2) TDRIVE_PD(2) TFALL_PD(2) TRISE_PD(3) TDRIVE_CPU_STOP#(2) TFALL_CPU_STOP#(2) TRISE_CPU_STOP#(3) Parameter Input HIGH Voltage Input LOW Voltage LOW Voltage, HIGH Threshold LOW Voltage, LOW Threshold Input HIGH Current Input LOW Current Input LOW Current Operating Supply Current Powerdown Current Input Frequency(1) Pin Inductance(2) Input Capacitance(2) Logic inputs Output pin capacitance XTAL_IN XTAL_OUT From VDD power-up or de-assertion of PD to first clock Triangular modulation SRC output enable after PCI_STOP# de-assertion CPU output enable after PD de-assertion Fall time of PD Rise time of PD CPU output enable after CPU_STOP# de-assertion Fall time of CPU_STOP# Rise time of CPU_STOP# 3.3V 5% 3.3V 5% For FSA.B.C test_mode For FSA.B.C test_mode VIN = VDD VIN = 0V, inputs with no pull-up resistors VIN = 0V, inputs with pull-up resistors Full active, CL = full load All differential pairs driven All differential pairs tri-stated VDD = 3.3V Test Conditions Min. 2 VSS - 0.3 0.7 VSS - 0.3 -5 -5 -200 -- -- -- -- -- -- -- -- -- -- 30 -- -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- 14.31818 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. VDD + 0.3 0.8 VDD + 0.3 0.35 5 -- -- 400 70 12 -- 7 5 6 5 12 1.8 33 15 300 5 5 10 5 5 ms KHz ns us ns ns us ns ns MHz nH pF Unit V V V V A A A mA mA
NOTES: 1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2. This parameter is guaranteed by design, but not 100% production tested. 3. See TIMING DIAGRAMS for timing requirements.
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR(1)
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 2pF
Symbol ZO VOH3 VOL3 VHIGH VLOW VOVS VUDS VCROSS(ABS) d - VCROSS ppm Parameter Current Source Output Impedance(2) Output HIGH Voltage Output LOW Voltage Voltage HIGH(2) Voltage LOW(2) Max Voltage(2) Min Voltage(2) Crossing Voltage (abs)(2) Crossing Voltage (var)(2) Long Accuracy(2,3)
Variation of crossing over all edges
Test Conditions VO = VX IOH = -1mA IOL = 1mA Statistical measurement on single-ended signal using oscilloscope math function Measurement on single-ended signal using absolute value
Min. 3000 2.4 -- 660 -300 -- -300 250 -- -300 2.4993 2.9991 3.7489 4.9985 5.9982 7.4978 9.997 10.4135 2.4143 2.9141 3.6639 4.9135 5.9132 7.4128 9.912 10.1635 175 175 -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max. -- -- 0.4 1150 150 1150 -- 550 140 300 2.5133 3.016 3.77 5.0266 6.032 7.54 10.0533 10.4198 -- -- -- -- -- -- -- -- 700 700 125 125 55
Unit V V mV mV mV mV ppm
See TPERIOD Min. - Max. values 400MHz nominal / -0.5% spread 333.33MHz nominal / -0.5% spread 266.66MHz nominal / -0.5% spread
TPERIOD
Average Period(3)
200MHz nominal / -0.5% spread 166.66MHz nominal / -0.5% spread 133.33MHz nominal / -0.5% spread 100MHz nominal / -0.5% spread 96MHz nominal 400MHz nominal / -0.5% spread 333.33MHz nominal / -0.5% spread 266.66MHz nominal / -0.5% spread 200MHz nominal / -0.5% spread 166.66MHz nominal / -0.5% spread 133.33MHz nominal / -0.5% spread 100MHz nominal / -0.5% spread 96MHz nominal
ns
TABSMIN
Absolute Min Period(2,3)
ns
tR tF d-tR d-tF dT3
Rise Time(2) Fall Time(2) Rise Time Variation(2) Fall Time Variation(2) Duty Cycle(2)
VOL = 0.175V, VOH = 0.525V VOL = 0.175V, VOH = 0.525V
ps ps ps ps %
Measurement from differential waveform
45
NOTES: 1. SRC clock outputs run only at 100MHz. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR, CONTINUED(1)
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 2pF
Symbol tSK3 Parameter Skew, CPU[1:0](2) Skew, CPU2(2) Skew, SRC(2) Jitter, Cycle to Cycle, CPU[1:0](2) tJCYC-CYC Jitter, Cycle to Cycle, CPU2(2) Jitter, Cycle to Cycle, Jitter, Cycle to Cycle, DOT96(2)
NOTES: 1. SRC clock outputs run only at 100MHz. 2. This parameter is guaranteed by design, but not 100% production tested.
Test Conditions VT = 50%
Min. -- -- -- --
Typ. -- -- -- -- -- -- --
Max. 100 250 250 85 100 125 250
Unit ps
Measurement from differential waveform
-- -- --
ps
SRC(2)
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 30pF
Symbol ppm TPERIOD VOH VOL IOH IOL Parameter Static Error(1,2) Clock Period(2) Output HIGH Voltage Output LOW Voltage Output HIGH Current Output LOW Current Edge Rate(1) Edge Rate(1) tR1 tF1 dT1 tSK1 tJCYC-CYC Rise Time(1) Fall Time(1) Duty Cycle(1) Skew(1) Jitter, Cycle to Cycle(1) Test Conditions See Tperiod Min. - Max. values 33.33MHz output nominal 33.33MHz output spread IOH = -1mA IOL = 1mA VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising edge rate Falling edge rate VOL = 0.8V, VOH = 2V VOL = 0.8V, VOH = 2V VT = 1.5V VT = 1.5V VT = 1.5V Min. -- 29.991 29.991 2.4 -- -33 -- 30 -- 1 1 0.3 0.3 45 -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 0 30.009 30.1598 -- 0.55 -- -33 -- 38 4 4 1.2 1.2 55 500 500 V/ns V/ns ns ns % ps ps mA V V mA Unit ppm ns
NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS, 48MHZ, USB
Symbol ppm TPERIOD VOH VOL IOH IOL Parameter Static Error(1,2) Clock Period(2) Output HIGH Voltage Output LOW Voltage Output HIGH Current Output LOW Current Edge Rate(1) Edge Rate(1) tR1 tF1 dT1 tJCYC-CYC Rise Time(1) Fall Time(1) Duty Cycle(1) Jitter, Cycle to Cycle Test Conditions See Tperiod Min. - Max. values 48MHz output nominal IOH = -1mA IOL = 1mA VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising edge rate Falling edge rate VOL = 0.8V, VOH = 2V VOL = 0.8V, VOH = 2V VT = 1.5V
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 20pF
Min. -- 20.8257 2.4 -- -29 -- 29 -- 1 1 0.5 0.5 45 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 0 20.834 -- 0.55 -- -23 -- 27 2 2 1.2 1.2 55 350 V/ns V/ns ns ns % ps mA Unit ppm ns V V mA
NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICAL CHARACTERISTICS - REF-14.318MHZ
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 20pF
Symbol ppm TPERIOD VOH VOL IOH IOL Parameter Long Accuracy(1) Clock Period Output HIGH Voltage(1) Output LOW Voltage(1) Output HIGH Current Output LOW Current Edge Rate(1) Edge Rate(1) tR1 tF1 dT1 tJCYC-CYC Rise Time(1) Fall Time(1) Duty Cycle(1) Jitter, Cycle to Cycle(1) Test Conditions See Tperiod Min. - Max. values 14.318MHz output nominal IOH = -1mA IOL = 1mA VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising edge rate Falling edge rate VOL = 0.8V, VOH = 2V VOL = 0.8V, VOH = 2V VT = 1.5V VT = 1.5V Min. -- 69.827 2.4 -- -33 -- 30 -- 1 1 0.3 0.3 45 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 0 69.855 -- 0.4 -- -33 -- 38 4 4 1.2 1.2 55 1000 V/ns V/ns ns ns % ps mA Unit ppm ns V V mA
NOTE: 1. This parameter is guaranteed by design, but not 100% production tested.
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PCI STOP FUNCTIONALITY
The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF[1:0] and SRC clocks can be set to be free-running through SMBus programming, they will ignore both the PCI_STOP# pin and the PCI_STOP register bit.
PCI_STOP# 1 0
CPU Normal Normal
CPU# Normal Normal
SRC Normal IREF * 6 or float
SRC# Normal Low
PCIF/PCI 33MHz Low
USB 48MHz 48MHz
DOT96 Normal Normal
DOT96# Normal Normal
REF 14.318MHz 14.318MHz
The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all PCI[6:0] and stoppable PCIF[1:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low, the SRC clock, (if set to stoppable) will latch high at IREF * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and the SRC# will latch low as shown below.
tSU
PCI_STOP# ASSERTION (TRANSITION FROM `1' TO `0')
PCI_STOP#
PCIF[1:0] 33MHz
PCI[3:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# - DE-ASSERTION
The de-assertion of the PCI_STOP# signal is to be sampled on the rising edge of the PCIF free running clock domain. After detecting PCI_STOP# de-assertion, all PCI[6:0], stoppable PCIF[1:0] and stoppable SRC clocks will resume in a glitch free manner.
tSU tDRIVE_SRC PCI_STOP#
PCIF[1:0] 33MHz
PCI[3:0] 33MHz
SRC 100MHz
SRC# 100MHz
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
CPU STOP FUNCTIONALITY
The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.
CPU Normal IREF * 6 or float CPU# Normal Low SRC Normal Normal SRC# Normal Normal PCIF/PCI 33MHz 33MHz USB 48MHz 48MHz DOT96 Normal Normal DOT96# Normal Normal REF 14.318MHz 14.318MHz
CPU_STOP# 1 0
Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the SMBus CPU_STOP tri-state bit corresponding to the CPU output of interest is programmed to a `0', CPU output will stop CPU_True = High and CPU_Complement = Low. When the SMBus CPU_STOP# tri-state bit corresponding to the CPU output of interest is programmed to a `1', CPU outputs will be tri-stated.
CPU_STOP# ASSERTION (TRANSITION FROM `1' TO `0')
CPU_STOP#
CPU
CPU#
CPU_STOP# - DE-ASSERTION (TRANSITION FROM `0' TO `1')
With the de-assertion of CPU_STOP# all stopped CPU outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs is two to six CPU clock periods. If the control register tristate bit corresponding to the output of interest is programmed to `1', then the stopped CPU outputs will be driven High within 10nS of CPU_STOP# de-assertion to a voltage greater than 200mV.
CPU_STOP#
CPU
CPU#
CPU Internal
tDRIVE_CPU_Stop 10nS > 200mV
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PD is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. When PD is asserted high all clocks will be driven low before turning off the VCO. In PD de-assertion all clocks will start without glitches.
PD 0 1 CPU Normal IREF * 2 or float CPU# Normal Float SRC Normal IREF * 2 or float SRC# Normal Float PCIF/PCI 33MHz Low USB 48MHz Low DOT96 Normal IREF * 2 or float DOT96# Normal Float REF 14.318MHz Low
PD, POWER DOWN
PD ASSERTION
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PD DE-ASSERTION
tSTABLE <1.8mS PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818 tDRIVE_PWRDWN <300S, <200mV
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or tristated during PD and CPU_STOP# mode and the SRC clock is configurable to be driven or tristated during PCI_STOP# and PD mode. Each differential clock (SRC, CPU[2:0]) output can be disabled by setting the corresponding output's register OE bit to "0" (disable). Disabled outputs are to be tristated regardless of "CPU_STOP", "SRC_STOP" and "PD" register bit settings.
Signal CPU CPU CPU CPU CPU Pin PD 0 0 0 1 1 Pin CPU_STOP# 1 0 0 X X CPU_STOPTristate Bit X 0 1 X X PD Tristate Bit X X X 0 1 Non-Stoppable Outputs Running Running Running Driven at IREF x 2 Tristate Stoppable Outputs Running Driven at IREF x 6 Tristate Driven at IREF x 2 Tristate
DIFFERENTIAL CLOCK TRISTATE
NOTES: 1. Each output has four corresponding control register bits; OE, PD, CPU_STOP, and "Free Running". 2. IREF x 6 and IREF x 2 is the output current in the corresponding mode. 3. See CONTROL REGISTERS section for bit address.
Signal SRC SRC SRC SRC SRC
Pin PD 0 0 0 1 1
Pin PCI_STOP# 1 0 0 X X
PCI_STOPTristate Bit X 0 1 X X
PD Tristate Bit X X X 0 1
Non-Stoppable Outputs Running Running Running Driven at IREF x 2 Tristate
Stoppable Outputs Running Driven at IREF x 6 Tristate Driven at IREF x 2 Tristate
NOTES: 1. SRC output has four corresponding control register bits; OE, PD, SRC_STOP, and "Free Running". 2. IREF x 6 and IREF x 2 is the output current in the corresponding mode. 3. See CONTROL REGISTERS section for bit address.
TRISTATE DOT96 CLOCK CONTROL
Signal DOT96 DOT96 DOT96 Pin PD 1 0 0 PD Tristate Bit X 0 1 Output Running Driven at IREF x 2 Tristate
NOTES: 1. DOT output has two corresponding control register bits; OE and PD. 2. IREF x 6 and IREF x 2 is the output current in the corresponding mode. 3. See CONTROL REGISTERS section for bit address.
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
LVDS AC TIMING REQUIREMENTS
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C
Symbol tR1 tF1 tR tF VHIGH VLOW VCROSS(ABS) VCROSS(REL) TOTAL VCROSS tJCYC-CYC dT3 VOVS VUDS VRB Parameter Clock Rise Time(1,2,3) Clock Fall Time(1,2,3) Clock Rise Time Variation(2,3,4) Clock Fall Time Variation(2,3,4) Rise/Fall Matching(2,3,5) Voltage HIGH(2,3,6) Voltage LOW (2,3,7) Crossing Voltage (abs)(2,3,8,9,10) Crossing Voltage (rel)(2,3,10,11) Total Variation of VCROSS Over All Edges(2,3,12) Cycle-to-Cycle Jitter(2,13) Duty Cycle(2,13) Maximum Voltage Allowed at Output (overshoot)(2,3,14) Minimum Voltage Allowed at Output (undershoot)(2,3,15) Ringback Margin(2,3) Min. 175 175 -- -- -- 660 -150 250 Calc. -- -- 45 -- -0.3 n/a Typ. -- -- -- -- -- 700 0 -- -- -- -- -- -- -- -- Max. 700 700 125 125 20 850 -- 550 Calc. 140 350 55 VHIGH + 0.3V -- 0.2 mV ps % V V V Unit ps ps ps ps % mV mV mV
NOTES: 1. Measured from VOL = 1.75V to VOH =0.525V. Only valid for Rising LVDS and Falling LVDS#. Signal must be monotonic through the VOL to VOH region for tRISE and tFALL. 2. Test configuration is Rs = 32.2, Rp = 49.9, 2pF. 3. Measurement taken from single-ended waveform. 4. Measured with oscilloscope, averaging off, using Min. Max. statistics. Variation is the delta between Min. and Max. 5. Measured with oscilloscope, averaging off, the difference between the tRISE (average) of LVDS versus the tFALL (average) of LVDS#. 6. VHIGH is defined as the statistical average HIGH value as obtained by using the oscilloscope VHIGH math function. 7. VLOW is defined as the statistical average LOW value as obtained by using the oscilloscope VLOW math function. 8. Measured at crossing point where the instantaneous voltage value of the rising edge of LVDS equals the falling edge of LVDS#. 9. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. 10. The crossing point must meet the absolute and relative crossing point specifications simultaniously. 11. VCROSS (rel) Min. and Max. are derived using the following: VCROSS (rel) Min. = 0.25V + 0.5 (VHAVG - 0.7V), VCROSS (rel) Max. = 0.55V + 0.5 (0.7V - VHAVG). 12. VCROSS is defined as the total variation of all crossing voltages of Rising LVDS and Falling LVDS#. This is the maximum allowed variance in VCROSS for any particular system. 13. Measurement is taken from differential waveform. 14. Overshoot is defined as the absolute value of the maximum voltage. 15. Undershoot is defined as the absolute value of the minimum voltage.
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IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
LVDS AVERAGE PERIOD, TPERIOD(1,2,3,4)
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C
Spread 0% (no spread) 0.8% down-spread 1% down-spread 1.25% down-spread 1.5% down-spread 1.75% down-spread 2% down-spread 2.5% down-spread 3% down-spread 0.3% down-spread 0.4% down-spread 0.5% down-spread 0.6% down-spread 0.8% down-spread 1% down-spread 1.25% down-spread 1.5% down-spread Min. 10.406 10.406 10.406 10.406 10.406 10.406 10.406 10.406 10.406 10.375 10.365 10.354 10.344 10.323 10.302 10.276 10.25 96MHz Max. 10.427 10.511 10.531 10.557 10.583 10.61 10.636 10.688 10.74 10.458 10.469 10.479 10.49 10.511 10.531 10.557 10.583 Min. 9.99 9.99 9.99 9.99 9.99 9.99 9.99 9.99 9.99 9.96 9.95 9.94 9.93 9.91 9.89 9.865 9.84 100MHz Max. 10.01 10.09 10.11 10.135 10.16 10.185 10.21 10.26 10.31 10.04 10.05 10.06 10.07 10.09 10.11 10.135 10.16 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Test configuration is Rs = 32.2, Rp = 49.9, 2pF. 2. The average period over any 1S period of tiime must be greater than the minimum and less than the maximum specified period. 3. Measurement is taken from differential waveform. 4. Calculated using a 0.1% accuracy in spread modulation. Assumes 300ppm long term accuracy on CLKIN.
tRISE (LVDS) VOH = 0.525V LVDS# VCROSS LVDS
VOL = 0.175V tFALL (LVDS#)
Single-Ended Measurement Point for tRISE and tFALL
20
IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
MISCELLANEOUS AC TIMING REQUIREMENTS
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C
Symbol tPZL tPZH tPLZ tPHZ tSTABLE tSPREAD All Clock Stabilization from Power-Up(2) Setting Period for Spread Selection Change
(2,3)
Parameter Output Enable Delay (All Outputs)
(1)
Min. 0 0 -- --
Typ. -- -- -- --
Max. 10 10 3 3
Unit s s ms ms
Output Disable Delay (All Outputs)(1)
NOTES: 1. These specifications apply to the LVDS and SMBus pins. These pins must be tri-stated when PWRDWN is asserted. LVDS is driven differential when PWRDWN is de-asserted unless it is disabled. 2. The time specified is from when VDD achieves its nominal operating level (typical condition VDD = 3.3V) and PWRDWN is de-asserted until the frequency output is stable and operating within specification. 3. The time specified is measured from the spread selection change or output frequency change until the LVDS clock is operating at the new spread modulation and frequency. If there is another change in spread selection or output frequency during the tSPREAD settling period, then the settling period start resets to the most recent change in spread selection and output frequency.
21
IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PWRDWN (POWER DOWN) CLARIFICATION
PWRDWN
CLOCK VCO
On
Off
LVDS
LVDS#
tPHZ
PWRDWN Assertion
VDD
PWRDWN
CLOCK VCO
Off
Starting tSTABLE
Stable
LVDS
LVDS#
tPZH
PWRDWN De-Assertion
22
IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
LVDS SYSTEM IMPLEMENTATION
Clock LVDS Clock Rs 33.2 5% Rp 49.9 1% Unit
33 5% CV125 LVDS TLA
Clock
33 5% LVDS# TLB
Clock#
475 1%
49.9 1%
49.9 1% 2pF 5% 2pF 5%
Test Load Board Configuration
23
IDTCV125 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
XXX IDTCV Device Type XX Package X Grade Blank Commercial Temperature Range (0C to +70C) Thin Small Shrink Outline Package TSSOP - Green Programmable FlexPC Clock for P4 Processor
PA PAG 125
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
24

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